PCI Express (PCIe)

PCI Express (PCIe) architecture is a serial I/O technology developed as the replacement interconnect bus for PCI and PCI-X. The technology defines a packetized protocol and a layered architecture. These properties, combined with signaling rates of 2.5 and 5.0 Gb/s per lane per direction, make PCIe architecture an ideal attach point for performance-intensive applications. Engineers working with this technology will find this high-speed multi-lane bus a challenge to test and debug without a PCI Express protocol analyzer.

The new and advanced Bus Doctor™ Gen 2 PCIe protocol analyzer supports bi-directional traffic capture and analysis of PCIe x1, x4 and x8 modes. Powerful pre-filtering and triggering options permit engineers to home in on any sequence of PCI events or conditions. In the x8 configuration, up to 18.4 GBs of capture buffer is available. With competing analyzers, such a large amount of memory would be problematic as searching for a PCIe event could take a substantial amount of time. However with JDSU's patented hardware search capability, this task can be performed within a matter of a few seconds.

The easy-to-use and intuitive Bus Doctor GUI software allows you to begin troubleshooting with the Bus Doctor minutes after you have hooked the analyzer to the PCIe system under test.

Effective performance, however, involves the entire system, not just the main system bus. With its broad support of computing protocols, the Bus Doctor is able to provide complete end-to-end visibility into the multi-protocol systems that comprise today's complex computing and storage applications. The Bus Doctor tracks packets across 14 different protocol standards– including USB, Serial ATA (SATA), Serial Attached SCSI (SAS), MMC/SD/SDIO and SCSI – enabling accurate correlation as well as full packet visibility at each crossover point.

Moreover, the PCIe analyzer can be used in conjunction with the signature Bus Doctor logic analysis feature allowing both PCIe and logic analysis to be performed at the same time.

The analyzer will accelerate design cycles and substantially improve time to market.

Product Features

Power Triggering - Enables you to create customized triggers with a trigger sequencer of 12 levels, including two timer levels and two counter levels so you can home in various PCIe events such as TLP and DLLP information and/or data payload
Large Capture Buffer – Supports up to 18.4 GBs of memory, more than twice the competing solution
Single Software Interface - Enables the user to learn one GUI for all bus types and test all bus types supported by Bus Doctor RX analyzer
Multi-Analysis - Allows multi-analysis on several buses simultaneously when the Bus Doctor PCIe Protocol Analyzer is used with other analyzers such as SAS, SATA and SCSI
Segmented Memory - The Capture Memory Buffer can be divided into up to 256 smaller segments, allowing up to 256 trace files to be captured and saved.
Timing Mode - Captures every PCIe transition or incoming channel change.
State Mode- Captures every single PCIe term that matches a pre-defined or customer created patterns
Real Time Statistics - Shows information for up to six PCIe terms as they occur, along with counters and bar graphs for each term. Each term may be viewed as occurrences-per-second, total occurrences, or occurrences-per-other-term
Post Capture Statistics - Shows PCIe statistics about the captured trace. Statistics can be calculated on individual PCIe terms or on the relationship between two PCIe terms
External Trigger In - Bus Doctor RX triggers may be generated either by the internal trigger sequencer or by external BNC input
External Trigger Out - The external BNC trigger out can be connected to other equipment, such as an oscilloscope, so that when the Bus Doctor RX triggers a signal is sent
PCIe Tree View – PCIe commands are shown in the order in which they occur. Each Command in the Tree View can be expanded to show PCIe responses, status, data, and other information
Customizable Views - The Command and State Listings can be customized. Fields can be added to the Command Listing to emphasize important PCIe fields for specific analysis or columns can be removed to simplify
Patented Hardware Search - Hardware search logic enables the user to search the entire memory buffer for any PCIe pattern in one second or less.